The present invention relates to frequency overshoot detection circuits, and, more particularly, to clock frequency overshoot detection circuits.
Electronic circuits such as microprocessors, microcontroller units (MCUs), system-on-chips (SOCs), and application specific integrated circuits (ASICs) are widely used in applications including industrial applications, automobiles, home appliances, and mobile and handheld devices. As an important safety critical example, MCUs are used to monitor and control critical functions in an automobile such as opening of airbags. Electronic circuits include a clock source (e.g. a phased-locked loop (PLL)) that generates a clock signal that is required for the functioning of the internal synchronous circuit elements (and certain external communication protocols) of the electronic circuit. However, the clock signal is prone to frequency overshoots when the clock source malfunctions due to an internal fault or an external disturbance. An increase in clock frequency beyond operating limits also can lead to functional failures of the electronic circuit.
Frequency overshoots may be caused for a number of reasons. Ionization and mechanical failure of crystals used in crystal oscillators, which are the primary source of the input clock to PLLs, lead to disturbances in the clock signal and introduce glitches in the clock signal. The closed loop nature of the PLL causes the output clock signal of the PLL to overshoot in frequency in response to the input glitches. Voltage-controlled oscillators (VCOs) are used to generate clock signals in a PLL. Unwanted fluctuations in the VCO gain or input voltage also may cause the clock frequency to overshoot. Additionally, dynamic circuit faults can lead to overshoots in the clock frequency.
Critical circuit or timing paths (logical connections of internal elements in an electronic circuit) are designed to operate at a maximum target frequency for the worst process, voltage and temperature (PVT) conditions, by applying a de-rating factor of about (+/−) 2% to the maximum frequency of operation. For example, for a circuit having a maximum operating frequency of 128 MHz, the critical circuit paths are timed to operate at a maximum frequency of 132 MHz. However, if the PLL clock frequency increases beyond the maximum frequency, the critical circuit paths may function erratically and introduce functional failures in the electronic circuit. Hence, it is important to detect clock signal frequency overshoots that are greater than the circuit's maximum frequency.
Various techniques are used to detect frequency overshoots in a clock signal. One such technique uses a combination of frequency comparators formed using counters and reference clocks (e.g. internal resistive-capacitive (RC) oscillators that are reliable compared to crystal oscillators) to detect overshoots in the clock frequency. The frequency comparator and the reference counter compare the input and feedback clock frequencies to detect frequency overshoots. Another technique uses clock monitoring circuits (including counters and reference clocks) to detect frequency overshoots in a clock signal. However, both of these techniques suffer from a slow response time, which is the time taken by a frequency overshoot detection circuit to detect an overshoot after the occurrence of the overshoot. The response time of existing systems is relatively high and varies in the range of a few 100 clock cycles. With such a slow response time, the frequency overshoots more often than not go undetected if the overshoot duration is small (e.g. 20-30 clock cycles). Since the electronic circuit can perform many operations in 20-30 clock cycles, it continues to operate with a bad clock signal, causing functional failures in critical timing paths and causing the electronic circuit to function erratically.
Therefore, it would be advantageous to have a clock frequency overshoot detection circuit with a fast response time. It further would be advantageous to have a clock frequency overshoot detection circuit that provides flexibility in design to eliminate the possibility of frequency overshoots going undetected. It also would be advantageous to have a clock frequency overshoot detection circuit that is simple, cost-effective, and reliable enough to overcome the above-mentioned drawbacks.